4.3.4 IP-based Interconnection

As a part of their work on high-speed networking, MIT also studied the processing costs associated with the use of the IP protocol for interconnecting different networks. They implemented an IP packet forwarder running with the x-kernel operating system on a MIPS 3000 33 MHz processor and measured resulting packet processing rates with and without network I/O drivers present.

After modifications to the x-kernel to reduce its overhead, a rate of 55 Kpackets/s was obtained with no I/O drivers installed. With the addition of an ethernet driver, throughput dropped to approximately 3 Kpackets/s, indicating that the dominant processing cost was associated with I/O rather than IP processing. Using IP instruction counts, they projected that the `pure' IP code processing on a 100 MHz RISC processor should approach 1Mpackets/s, allowing a flow of packet sizes as small as 83 Bytes to fully utilize a 622 Mbps link.

Based on these results, they designed an architecture for a high performance IP flow forwarder which makes use of multiple RISC processors. One processor is dedicated to IP level processing for each flow direction, one processor performs background management tasks, and one processor is dedicated to each flow direction of each I/O port. Thus, a forwarder providing full duplex connections between two networks has a total of 7 processors. Both a central memory and distributed memory architectures were considered, with the choice depending in part on the number of networks connected to the forwarder.

Conclusions drawn by MIT from this work were that, to scale routers up for very high speed networks, new designs should focus on providing increased hardware assistance in conjunction with RISC processing at individual ports and will need to evolve from shared memory to parallel switching fabrics for port interconnection. They also observed that the latter interconnect architecture will make it more difficult to implement global resource management, since information and control is now distributed among the port elements.